Job Details

High-speed Interface Micro Architect and RTL Design Engineer

Company
Qualcomm Technologies, Inc.

Job Area
Engineering Group > ASICS Engineering

General Summary
The Mixed-Signal IP team at Qualcomm is seeking skilled digital design engineers to contribute to the development of next-generation, high-performance, low-power interface IPs—including SerDes, DDR, and die-to-die interconnects—for integration across Qualcomm's product portfolio. In this role, you will collaborate with a cross-functional team to architect, design, implement, and validate complex IP blocks. Your work will directly support multiple business units and require a strong grasp of the full ASIC design flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor technologies.

Responsibilities

• Architect and define the digital design of high-speed interface IPs (e.g., SerDes, DDR, die-to-die) in close collaboration with system architecture and analog teams
• Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
• Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA)
• Utilize industry-standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design‑for‑test (DFT), synthesis, formal verification (FV), and static timing analysis (STA)
• Design and analyze DFT logic, including ATPG for stuck‑at fault (SAF) and transition delay fault (TDF) coverage
• Create comprehensive design documentation, including hardware specifications
• Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs
• Work with the physical design (PD) team to support floorplanning, placement, and timing closure of IPs
• Support SoC integration and debug, including pre‑silicon simulation and post‑silicon bring‑up

Required for This Role

• Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of hands‑on experience in micro‑architecture and digital design for mixed‑signal IPs such as SerDes, DDR, PLLs, DACs, ADCs, and sensors
• Proficiency with industry‑standard ASIC design tools including Design Compiler, PrimeTime, Power Compiler (PTPX), VCS, DFT Compiler, Spyglass, and others

Preferred Qualifications

• Ph.D. in Electrical Engineering with 3+ years of industry experience in high‑speed digital circuit design
• Strong background in low‑power digital design techniques
• Expertise in computer architecture, digital signal processing, and algorithm development
• Experience developing automation scripts and design productivity tools using Python or Perl

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• or Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• or PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Pay Range
$164,000.00 – $246,000.00

EEO Statement
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail ...@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).